Memory-level parallelism

Results: 20



#Item
11Computer engineering / Cache / CPU cache / Computer memory / Microarchitecture / Out-of-order execution / Instruction-level parallelism / Pentium Pro / Parallel computing / Computer architecture / Computer hardware / Central processing unit

Appeared in the Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October[removed]Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors Parthas

Add to Reading List

Source URL: barroso.org

Language: English - Date: 2005-03-07 23:35:18
12Electronic engineering / CPU cache / Cache / Central processing unit / Leakage / Dynamic voltage scaling / Memory hierarchy / Intel Core / Computer hardware / Computer memory / Electrical engineering

Journal of Instruction-Level Parallelism[removed]Submitted 10/02; published 4/03

Add to Reading List

Source URL: www.jilp.org

Language: English - Date: 2003-04-27 18:43:38
13Central processing unit / CPU cache / Cache / Software optimization / Memory hierarchy / R10000 / Lookup table / Memory disambiguation / R8000 / Computer memory / Computing / Computer hardware

Journal of Instruction-Level Parallelism[removed]Submitted 10/02; published 4/03

Add to Reading List

Source URL: www.jilp.org

Language: English - Date: 2003-04-27 18:43:27
14Central processing unit / Classes of computers / Computer memory / Parallel computing / CPU cache / Superscalar / Cache / Reduced instruction set computing / Instruction-level parallelism / Computer hardware / Computer architecture / Computing

SIMULATING SOME ADVANCED PROCESSING TECHNIQUES INTO A SUPERSCALAR ARCHITECTURE

Add to Reading List

Source URL: webspace.ulbsibiu.ro

Language: English - Date: 2010-05-17 01:41:51
15Central processing unit / Branch predictor / CPU cache / Microarchitecture / Memory-level parallelism / Register renaming / Superscalar / DEC Alpha / Computer performance / Computer architecture / Computer hardware / Computer engineering

Energy-Performance Design Space Exploration in SMT Architectures Exploiting Selective Load Value Predictions A. Gellert1 G. Palermo2

Add to Reading List

Source URL: webspace.ulbsibiu.ro

Language: English - Date: 2010-02-24 17:04:56
16Central processing unit / CPU cache / Cache / Computer memory / Branch predictor / Microarchitecture / Parallel computing / Superscalar / Instruction-level parallelism / Computer architecture / Computer hardware / Computer engineering

060-computer-Geller[removed]

Add to Reading List

Source URL: webspace.ulbsibiu.ro

Language: English - Date: 2007-12-05 00:43:29
17Central processing unit / Computer memory / Runahead / CPU cache / Microarchitecture / Memory-level parallelism / Parallel computing / Branch predictor / Instruction set / Computer architecture / Computer hardware / Computer engineering

059-computer-Florea[removed]

Add to Reading List

Source URL: webspace.ulbsibiu.ro

Language: English - Date: 2007-12-05 00:43:29
18Central processing unit / CPU cache / Cache / Computer memory / Parallel computing / Microarchitecture / Branch predictor / Superscalar / Instruction-level parallelism / Computer architecture / Computer hardware / Computing

Trace Cache Leon Gu Dipti Motiani

Add to Reading List

Source URL: www.cs.cmu.edu

Language: English - Date: 2003-10-13 07:06:40
19Computing / Microprocessors / Memory-level parallelism / Cache / CPU cache / Microarchitecture / Multithreading / MLP / Parallel computing / Computer architecture / Computer hardware / Central processing unit

MLP yes! ILP no!

Add to Reading List

Source URL: www.cs.berkeley.edu

Language: English - Date: 1998-10-18 20:47:54
20Central processing unit / Threads / Microprocessors / Memory-level parallelism / Runahead / Parallel computing / Simultaneous multithreading / Branch predictor / Multithreading / Computer architecture / Computer hardware / Computing

PDF Document

Add to Reading List

Source URL: users.elis.ugent.be

Language: English - Date: 2010-06-28 07:19:43
UPDATE